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asahi kasei [ak5394a] ms0137-e-01 2002/07 - 1 - general description the ak5394a is a 24bit, 192khz sampling 2ch a/d converter for professional digital audio systems. the modulator in the ak5394a uses the new developed advanced multi bit architecture. this new architecture achieves the wide dynamic range and wide bandwidth, while keeping superior distortion characteristics. the ak5394a performs 123db dynamic range, so the device is suitable for professional studio equipment such as digital mixer, digital vtr etc. the operating voltages support analog 5v and digital 3.3v, so it is easy to i/f with 3.3v logic ic. features ? 128x oversampling ? new advanced multi bit architecture adc ? sampling rate: 1khz 216khz ? full differential inputs ? s/(n+d): 110db ? dr: 123db ? s/n: 123db ? high performance linear phase digital anti-alias filter ? passband: 0 21.768khz(@fs=48khz) ? ripple: 0.001db ? stopband: 120db ? digital hpf & offset calibration for offset cancel ? power supply: 5v 5%(analog), 3 5.25v(digital) ? power dissipation: 665mw ? package: 28pin sop ? ak5392/3 semi-pin compatible lrck vrefl+ vrefl- sclk smode1 fsync serial output interface smode2 dgnd va agnd bgnd cal rstn vd controller sdata mclk dfs0 hpfe zcal ainr- vrefr- delta-sigma modulator voltage reference decimation filter hpf hpf calibration sram vcom l ainl+ ainl- ainr+ vcomr vrefr+ 12 11 14 13 16 15 19 17 18 8 7 10 9 21 22 23 27 28 26 24 25 6 5 4 3 2 1 dfs1 20 delta-sigma modulator voltage reference decimation filter ak5394a super high performance 192khz 24-bit ? adc
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 2 - ? ordering guide AK5394AVS ?10 +70 c 28pin sop akd5394a ak5394a evaluation board ? pin layout 6 5 4 3 2 1 vrefl+ vrefl- ainl+ vcoml ainl- zcal vd 7 dgnd 8 top view 10 9 cal rstn smode2 11 smode1 12 13 14 lrck sclk vrefr+ vrefr- vcomr ainr+ ainr- va agnd bgnd dfs1 hpfe dfs0 mclk 23 24 25 26 27 28 22 21 19 20 18 17 16 15 fsync sdata ? compatibility with ak5392/3 ak5394a ak5393 ak5392 pin 2 vrefl ? gndl gndl pin 18 dfs0 dfs cmode pin 20 dfs1 test test pin 27 vrefr ? gndr gndr fs (max) 216khz 108khz 54khz mclk at 48khz 256fs 256fs 256fs or 384fs mclk at 96khz 128fs 128fs n/a mclk at 192khz 64fs n/a n/a dr 123db 117db 116db s/n 123db 117db 116db
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 3 - ? common pcb layout example between ak5393 and ak5394a pin# ak5393 ak5394a gndl vrefl ? 2 connected to agnd connected to agnd with a 10uf electrolytic capacitor, and connected to vrefl+ with a 0.22uf ceramic capacitor. 18 dfs dfs0 20 test dfs1 gndr vrefr ? 27 connected to agnd connected to agnd with a 10uf electrolytic capacitor, and connected to vrefr+ with a 0.22uf ceramic capacitor. 0.1u 0.22u + 10u vrefl+ 1 gndl 2 vcoml 3 ainl+ 4 ainl- 5 zcal 6 vd 7 dgnd 8 cal 9 rstn 10 smode2 11 smode1 12 vrefr+ 28 gndr 27 vcomr 26 ainr+ 25 ainr- 24 va 23 agnd 22 bgnd 21 test 20 hpfe 19 dfs 18 mclk 17 ak5393 13 14 16 15 lrck sclk fsync sdata +3.3~5v digital 10u + 0.1u +5v analog 0.1u 0.1u (short ) 0.22u 10u + + 10u 0.22u 10u + 0.22u + 10u vrefl+ 1 vrefl- 2 vcoml 3 ainl+ 4 ainl- 5 zcal 6 vd 7 dgnd 8 cal 9 rstn 10 smode2 11 smode1 12 vrefr+ 28 vrefr- 27 vcomr 26 ainr+ 25 ainr- 24 va 23 agnd 22 bgnd 21 dfs1 20 hpfe 19 dfs0 18 mclk 17 ak5394a 13 14 16 15 lrck sclk fsync sdata +3.3~5v digital 10u + 0.1u +5v analog 0.1u 0.22u 10u 0.22u 10u + + + 10u (short ) (analog ground ) (analog ground )
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 4 - pin/function no. pin name i/o function 1 vrefl+ o lch positive reference voltage, 3.75v normally connected to agnd with a large electrolytic capacitor and connected to vrefl ? with a 0.22 f ceramic capacitor. 2 vrefl ? o lch negative reference voltage, 1.25v normally connected to agnd with a large electrolytic capacitor and connected to vrefl+ with a 0.22 f ceramic capacitor. 3 vcoml o lch common voltage pin, 2.75v 4 ainl+ i lch analog positive input pin 5 ainl- i lch analog negative input pin 6 zcal i zero calibration control pin this pin controls the calibration reference signal. ?l? :vcoml and vcomr ?h? : analog input pins (ainl , ainr ) 7 vd - digital power supply pin, 3.3v 8 dgnd - digital ground pin, 0v 9 cal o calibration active signal pin ?h? means the offset calibration cycle is in progress. offset calibration starts when rstn pin goes ?h?. cal goes ?l? after 8704 lrck cycles for dfs pin = ?l?, 17408 lrck cycles for dfs pin = ?h?. 10 rstn i reset pin when ?l?, the digital section is powered-down. upon returning ?h?, an offset calibration cycle is started. an offset calibration cycle should always be initiated after power-up. 11 12 smode2 smode1 i i serial interface mode select pin msb first, 2?s compliment. smode2 smode1 mode lrck l l slave mode : msb justified : h/l l h master mode : similar to i 2 s : h/l h l slave mode : i 2 s : l/h h h master mode : i 2 s : l/h 13 lrck i/o left/right channel select clock pin when rstn pin = ?l? in master mode, lrck outputs ?l?.
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 5 - 14 sclk i/o serial data clock pin sdata is clocked out on the falling edge of sclk. slave mode: sclk requires more than 48fs clock. master mode: ak5394a outputs following clocks as sclk. normal speed mode: 128fs double speed mode: 64fs quad speed mode: 64fs when rstn pin = ?l?, sclk outputs ?l?(normal/double speed mode) or outputs the inverted mclk (quad speed mode). 15 sdata o serial data output pin msb first, 2?s complement. 16 fsync i/o frame synchronization signal pin slave mode: when ?h?, the data bits are clocked out on sdata. in i 2 s mode, fsync is don?t care. master mode: fsync outputs 2fs clock. fsync stays ?l? during reset. 17 mclk i master clock input pin dfs1 dfs0 mclk fs(typ) l l 256fs 48khz l h 128fs 96khz h l 64fs 192khz h h (n/a) (n/a) 18 dfs0 i sampling speed select pin 0 dfs1 dfs0 fs(typ) l l 48khz l h 96khz h l 192khz h h (n/a) 19 hpfe i high pass filter enable pin ?l?: disable ?h?: enable 20 dfs1 i sampling speed select pin 1 (see #18 dfs0) 21 bgnd - substrate ground pin, 0v 22 agnd - analog ground pin, 0v 23 va - analog supply pin, 5v 24 ainr ? i rch analog negative input pin 25 ainr+ i rch analog positive input pin 26 vcomr o rch common voltage pin, 2.75v 27 vrefr ? o rch negative reference voltage, 1.25v normally connected to agnd with a large electrolytic capacitor and connected to vrefr+ with a 0.22 f ceramic capacitor. 28 vrefr+ o rch positive reference voltage, 3.75v normally connected to agnd with a large electrolytic capacitor and connected to vrefr- with a 0.22 f ceramic capacitor. note: all digital inputs should not be left floating.
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 6 - absolute maximum ratings (agnd, bgnd, dgnd = 0v; note 1) parameter symbol min max units power supplies: analog digital |bgnd-dgnd| (note 2) va vd ? gnd ? 0.3 ? 0.3 - 6.0 6.0 0.3 v v v input current, any pin except supplies iin - 10 ma analog input voltage vina ? 0.3 va+0.3 v digital input voltage vind ? 0.3 vd+0.3 v ambient temperature (power applied) ta ? 10 70 c storage temperature tstg ? 65 150 c notes: 1. all voltages with respect to ground. 2. agnd, bgnd and dgnd must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd, bgnd, dgnd = 0v; note 1) parameter symbol min typ max units power supplies: analog (note 3) digital va vd 4.75 3.0 5.0 3.3 5.25 5.25 v v notes: 1. all voltages with respect to ground. 3. the power up sequence between va and vd is not critical. * akm assumes no responsibility for the usage beyond the conditions in this data sheet.
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 7 - analog characteristics (ta = 25 c; va=5.0v; vd=3.3v; agnd=bgnd=dgnd=0v; fs=48khz; signal frequency=1khz; 24bit output; measurement frequency=10hz 20khz; dfs0=?l?, dfs1=?l?; external circuit: figure 9 inputted through xlr; unless otherwise specified) parameter min typ max units resolution 24 bits analog input characteristics: fs=48khz ? 1dbfs (note4) ? 1dbfs ? 20dbfs ? 60dbfs - 87 - - 110 94 100 60 db db db db fs=96khz bw=40khz ? 1dbfs (note4) ? 1dbfs ? 20dbfs ? 60dbfs - 87 - 110 94 97 57 db db db db s/(n+d) fs=192khz bw=80khz ? 1dbfs ? 20dbfs ? 60dbfs - - - 94 92 52 db db db dynamic range (-60dbfs with a-weighted) (note4) 117 - 123 120 db db s/n ( a-weighted) (note4) 117 - 123 120 db db interchannel isolation 110 120 db interchannel gain mismatch 0.1 0.5 db gain drift 150 ppm/ c offset error after calibration, hpf=off after calibration, hpf=on 1000 1 - - lsb 24 lsb 24 offset drift (hpf=off) - 10 - lsb 24 / c offset calibration range (hpf=off) (note5) 50 mv input voltage (ain+) ? (ain ? ) 2.25 2.4 2.55 v power supplies: power supply current va vd (fs=48khz; dfs0=?l?, dfs1=?l?) (fs=96khz; dfs0=?h?, dfs1=?l?) (fs=192khz; dfs0=?l?, dfs1=?h?) 127 9 13 21 165 13.5 20 32 ma ma ma ma power dissipation 665 870 mw power supply rejection (note 6) 70 db notes: 4. using the circuit as shown in figure9 (analog input buffer circuit example 1). 1000f capacitors connected between vref+/ ? pin and gnd. 5. the output level reduces equivalent to dc offset after calibration. 6. psrr is applied to va and vd with 1khz, 20mvpp.
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 8 - filter characteristics (fs=48khz) (ta=25 c; va=5.0v 5%; vd=3.0 5.25v; fs=48khz, dfs0=?l?, dfs1=?l?) parameter symbol min typ max units adc digital filter(decimation lpf): passband (note 7) pb 0 21.768 khz stopband (note 7) sb 26.232 khz passband ripple pr 0.001 db stopband attenuation (note 8) sa 120 db group delay distortion ? gd 0 s group delay (note 9) gd 63 1/fs adc digital filter(hpf): frequency response (note 7) ? 3db ? 0.1db fr 1.0 6.5 hz hz filter characteristics (fs=96khz) (ta=25 c; va=5.0v 5%; vd=3.0 5.25v; fs=96khz, dfs0=?h?, dfs1=?l?) parameter symbol min typ max units adc digital filter(decimation lpf): passband (note 7) pb 0 43.536 khz stopband (note 7) sb 52.464 khz passband ripple pr 0.003 db stopband attenuation (note 10) sa 120 db group delay distortion ? gd 0 s group delay (note 9) gd 63 1/fs adc digital filter(hpf): frequency response (note 7) ? 3db ? 0.1db fr 1.0 6.5 hz hz filter characteristics (fs=192khz) (ta=25 c; va=5.0v 5%; vd=3.0 5.25v; fs=192khz, dfs0=?l?, dfs1=?h?) parameter symbol min typ max units adc digital filter(decimation lpf): passband (note 7) pb 0 87.072 khz stopband (note 8) sb 104.928 khz passband ripple pr 0.007 db stopband attenuation (note 11) sa 120 db group delay distortion ? gd 0 s group delay (note 9) gd 63 1/fs adc digital filter(hpf): frequency response (note 7) ? 3db ? 0.1db fr 1.0 6.5 hz hz
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 9 - notes: 7. the passband and stopband frequencies are proportional to fs. 8. the analog modulator samples the input at 6.144mhz for an output word rate of 48khz. there is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 6.144mhz 21.768khz, where n=1,2,3). 9. the calculating delay time which takes place due to the digital filtering process. this time is taken from when the analog signal ia input, to the time of setting the 24-bit data (from both channels) to the output register. 65/fs typ. (normal/double/quad speed mode) at hpf=on. 10. the analog modulator samples the input at 6.144mhz for an output word rate of 96khz. there is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 6.144mhz 43.536khz, where n=1,2,3) 11. the analog modulator samples the input at 6.144mhz for an output word rate of 192khz. there is no rejection of input signals which are multiples of the sampling frequency (that is: there is no rejection for n x 6.144mhz 87.072khz, where n=1,2,3). digital characteristics (ta=25 c; va=5.0v 5%; vd = 3.0 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%vd - - - - 30%vd v v high-level output voltage iout=-100 a low-level output voltage iout= 100 a voh vol vd ? 0.5 - - - 0.5 v v input leakage current iin - - 10 a
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 10 - switching characteristics (ta=25 c; va=5.0v 5%; vd=3.0 5.25v; c l =20pf) parameter symbol min typ max units control clock frequency master clock pulse width low pulse width high serial data output clock (sclk) channel select clock (lrck) duty cycle fclk tclkl tclkh fslk fs 0.256 29 29 1 25 12.288 6.144 48 13.824 13.824 216 75 mhz ns ns mhz khz % serial interface timing (note 12) slave mode (smode1 = ?l?) sclk period (note 13) normal speed mode double speed mode quad speed mode sclk pulse width low pulse width high sclk rising to lrck edge (note 14) lrck edge to sclk rising (note 14) lrck edge to sdata msb valid sclk falling to sdata valid sclk falling to fsync edge tslk tslk tslk tslkl tslkh tslr tlrs tdlr tdss tsf 1/128fs 1/64fs 1/64fs 33 33 20 20 ? 20 20 20 20 ns ns ns ns ns ns ns ns ns ns master mode (smode1 = ?h?) sclk frequency normal speed mode double speed mode quad speed mode sclk duty cycle fsync frequency fsync duty cycle sclk falling to lrck edge lrck edge to fsync rising sclk falling to sdata valid sclk falling to fsync edge fslk fslk fslk dslk ffsync dfsync tmslr tlrf tdss tsf ? 20 ? 20 128fs 64fs 64fs 50 2fs 50 1 20 20 20 hz hz hz % hz % ns tslk ns ns reset / calibration timing rstn pulse width rstn falling to cal rising rstn rising to cal falling (note 15) normal speed mode double speed mode quad speed mode rstn rising to sdata valid (note 15) normal speed mode double speed mode quad speed mode trtw trcr trcf trcf trcf trtv trtv trtv 150 8704 17408 34816 8719 17423 34831 50 ns ns 1/fs 1/fs 1/fs 1/fs 1/fs 1/fs notes: 12. refer to serial data interface section. 13. at slave mode, sclk must be continuously provided more than 16fs at lrck=?h? and ?l?. 14. specified lrck edges not to coincide with the rising edges of sclk. 15. the number of the lrck rising edges after rstn pin brought high.
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 11 - ? timing diagram lrck sclk sdata tdss tslr tslkl tslkh tslk tdlr msb msb-1 msb-2 tlrs serial data timing (slave mode, fsync = ?h?) lrck sclk tslr tsf sdata tdlr msb d1 d0 tsf tdss fsync tlrs serial data timing (slave mode) lrck sclk sdata tdss tslr tslkl tslkh tslk msb msb-1 tdss tlrs serial data timing (i 2 s slave mode, fsync = don?t care)
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 12 - lrck sclk tmslr tsf sdata msb-1 tsf tdss msb fsync tlrf serial data timing (master mode & i 2 s master mode, normal speed mode) rstn sdata trtv trcr cal trtw trcf reset & calibration timing
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 13 - operation overview ? system clock input the external clocks that are required to operate the ak5394a are mclk, lrck(fs) and sclk. mclk should be synchronized with lrck but the phase is free of care. table 1 and 2 show the relationship between the sampling rate and the frequencies of mclk and sclk. as the ak5394a includes the phase detect circuit for lrck, the ak5394a is reset automatically when the synchronization is out of phase by changing the clock frequencies. therefore, the reset is only needed for power-up. all external clocks must be present unless rstn pin = ?l?, otherwise excessive current may result from abnormal operation of internal dynamic logic. sampling speed normal double quad dfs0 l h l dfs1 l l h lrck (fs) 54khz 108khz 216khz sclk (slave mode) 128fs 64fs 64fs sclk (master mode) 128fs 64fs 64fs mclk 256fs 128fs 64fs table 1. system clocks lrck (fs) mclk sclk 32khz 8.1920mhz 4.0960mhz 44.1khz 11.2896mhz 5.6448mhz 48khz 12.2880mhz 6.1440mhz 96khz 12.2880mhz 6.1440mhz 192khz 12.2880mhz 12.288mhz table 2. examples of system clock frequency ? serial data interface the ak5394a supports four serial data formats that can be selected via smode1 and smode2 pins (table 3). the data format is msb-first, 2?s complement. figure smode2 smode1 mode lrck figure 1 l l slave mode lch = h, rch = l figure 2 l h master mode lch = h, rch = l figure 3 h l i 2 s slave mode lch = l, rch = h figure 4 h h i 2 s master mode lch = l, rch = h table 3. serial i/f formats
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 14 - lrck ( i ) sclk(i) 012 2021232415 01 20222325 0 1 25 22 21 24 lch data rch data sdata(o) 23 22 23 21 7 42 43 20 1 21 22 310 3 23 fsync(i) fsync ( i ) 23 23 22 5 3 54 310 2 22 4210 22 23 23 sdata ( o ) 23:msb,0:lsb figure 1. serial data timing (slave mode) lrck ( o ) sclk ( o ) 0 1 2 20 21 23 24 15 34 3 20 21 23 0 1 25 22 2 22 3 01 fsync(o) 23 23 5 3 54 310 2 22 4210 23 sdata(o) lch data 33 25 24 33 34 22 23:msb,0:lsb rch data figure 2. serial data timing (master mode, normal speed mode) lrck ( i ) sclk ( i ) 012 19202223 01 19212224 0 1 24 21 20 23 3 23 23 23 22 6 4 65 421 3 22 5 3 21 23 sdata ( o ) lch data rch data 23:msb,0:lsb 0 0 figure 3. serial data timing (i 2 s slave mode, fsync: don?t care) lrck ( o ) sclk ( o ) 0 1 2 20 21 23 24 15 34 3 20 21 23 0 1 25 22 2 22 3 01 fsync ( o ) 23 23 23 5 3 54 310 2 22 4210 23 sdata ( o ) lch data rch data 33 25 24 33 34 22 23:msb,0:lsb figure 4. serial data timing (i 2 s master mode, normal speed mode)
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 15 - ? offset calibration 1. when the capacitors of 10f or less are connected between vref pin and gnd: when rstn pin goes to ?l?, the digital section is powered-down. upon returning ?h?, the offset calibration cycle is started. the offset calibration cycle should always be initiated after power-up. during the offset calibration cycle, the digital section of the part measures and stores the values of calibration input of eac h channel in registers. the calibration input value is subtracted from all future outputs. the calibration input may be obtained from either the analog input pins (ain+/ ? ) or the vcom pins depending on the state of the zcal pin. with zcal ?h?, the analog input pin voltages are measured, and with zcal ?l?, the vcom pin voltages are measured. the cal output is ?h? during calibration. 2. when capacitors more than 10f are connected between vref pin and gnd: the distortion at low frequency can be improved by connecting large capacitors (c in figure 5) to vref pins. (refer to figure 12) however, when the capacitors of vref pins are larger than 10f, it is possibility that the offset calibration does not performed correctly if the offset calibration cycle is started right after power-up. because the internal vref can not settle to the appropriate voltage when the calibration cycle is completed. in this case, the offset calibration cycle should be started again after the vref voltage settled. the timing is shown in figure 6. table 4 shows the relationship between the capacitance and the vref settling time. capacitor c[ f] settling time t[s]=5000 x c 1000 5 470 2.4 220 1.1 100 0.5 table 4. settling time and capacitors connected between vref and gnd vrefl+ 1 vrefl- 2 0.22u c + ak5394a + c figure 5. vref circuit example
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 16 - rstn sdata trtv trcr cal trtw trcf va, vd settling time of vref pin:t(s) 0.005 x c 150ns~1ms figure 6. reset & calibration timing ? digital high pass filter the ak5394a includes a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is 1hz at fs=48khz (normal speed mode), at fs=96khz (double speed mode), at fs=192khz (quad speed mode) and also scales with sampling rate (fs) respectively. sampling speed dfs1 dfs0 fc (cut-off frequency) normal l l fs/48khz double l h fs/96khz quad h l fs/192khz table 5. cut-off frequency
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 17 - system design figure 7 and 8 show the system connection diagram. an evaluation board [akd5394a] is available which demonstrates the optimum layout, power supply arrangements and measurement results. vrefl+ 1 vrefl- 2 vcoml 3 ainl+ 4 ainl- 5 zcal 6 vd 7 dgnd 8 cal 9 rstn 10 smode2 11 smode1 12 vrefr+ 28 vrefr- 27 vcomr 26 ainr+ 25 ainr- 24 va 23 agnd 22 bgnd 21 dfs1 20 hpfe 19 dfs0 18 mclk 17 0.22u c + ak5394a 13 14 16 15 lrck sclk fsync sdata 0.22u lch+ +3.3~5v digital rch+ rch- 0.22u reset & cal control 10u + 0.1u system controller mode select +5v analog + 0.1u 10u 0.22u c lch- fs analog ground system ground + c + + c figure 7. typical connection diagram notes: - lrck = fs, sclk = 64fs. - power lines of va and vd should be distributed separately from the point with low impedance of regulator etc. - agnd, bgnd and dgnd must be connected to the same analog ground plane. - all digital input pins should not be left floating. - refer table 4 and figure 12 about c. analog ground digital ground system controller vrefl+ 1 vrefl- 2 vcoml 3 ainl+ 4 ainl- 5 zcal 6 vd 7 dgnd 8 cal 9 rstn 10 smode 11 mcks 12 vrefr+ 28 vrefr- 27 vcomr 26 ainr+ 25 ainr- 24 va 23 agnd 22 bgnd 21 dfs1 20 hpfe 19 dfs0 18 mclk ak5394a 17 13 14 16 15 lrck sclk fsync sdata figure 8 ground layout
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 18 - 1. grounding and power supply decoupling the ak5394a requires careful attention to power supply and grounding arrangements. analog ground and digital ground of the system should be separate and connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak5394a as possible, with the small value ceramic capacitor being the nearest. 2. on-chip voltage reference and vcom the reference voltage for a/d converter is supplied from vref+/ ? pin at agnd reference. a 0.22f ceramic capacitor should be attached between vref+ and vref ? . an electrolytic capacitor (<1000f) should be connected between agnd and vref+/ ? respectively to eliminate the effects of low frequency noise. especially a ceramic capacitor should be as near to the pins as possible. and all digital signals, especially clocks, should be kept away from the vref+/ ? pins in order to avoid unwanted coupling into the ak5394a. no load current may be taken from the vref+/ ? pins. vcom is a common voltage of the analog signal. in order to eliminate the effects of high frequency noise, a 0.22f ceramic capacitor should be connected as near to the vcom pin as possible. and all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the ak5394a. no load current may be drawn from the vcom pin. 3. analog inputs analog signal is differentially input into the modulator via the ain+ and the ain ? pins. the input voltage is the difference between ain+ and ain ? pins. the full-scale of each pin is nominally 2.4vpp (typ). the ak5394a can accept input voltages from agnd to va. the adc output data format is 2?s complement. the output code is 7fffffh (@24bit) for input above a positive full scale and 800000h (@24bit) for input below a negative full scale. the ideal code is 000000h (@24bit) with no input signal. the dc offset is removed by the offset calibration. the ak5394a samples the analog inputs at 128fs (6.144mhz@fs=48khz, normal speed mode). the digital filter rejects noise above the stop band except for multiples of 128fs. a simple rc filter may be used to attenuate any noise around 128fs and most audio signals do not have significant energy at 128fs. the ak5394a accepts +5v supply voltage. any voltage which exceeds the upper limit of va+0.3v and lower limit of agnd ? 0.3v and any current beyond 10ma for the analog input pins (ain+/ ? ) should be avoided. excessive currents to the input pins may damage the device. hence input pins must be protected from signals at or beyond these limits. use caution specially in case of using 15v in other analog circuits.
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 19 - 4. external analog circuit figure 9 shows an input buffer circuit example 1. (1 st order hpf; fc=0.70hz, 2 nd order lpf; fc=320khz, gain= ? 14.5db). the analog signal is able to input through xlr or bnc connectors. (short jp1 and jp2 for bnc input, open jp1 and jp2 for xlr input). the input level of this circuit is +/ ? 12.7vpp (ak5394a: +/ ? 2.4vpp typ.). when using this circuit, analog characteristics at fs=48khz is dr=120db, s/(n+d)=105db. 4.7k - + - + 91 3.3k 620 - + 91 620 analog in 12.7vpp 68 njm5534 va=+5v vp= 15v 4.7k 10 + 10k 10k 0.1 bias va+ 2.4vpp 2.4vpp vp+ vp- bias 1n 3.3k 1n bias 2.2n 68 xlr vin+ vin- jp1 jp2 njm5534 njm5534 ak5394 ain+ ak5394 ain- figure 9. analog input buffer circuit example 1 fin 1hz 10hz frequency response ? 1.77db ? 0.02db table 6. frequency response of hpf fin 20khz 40khz 80khz 6.144mhz frequency response 0.00db 0.00db 0.00db ? 51.36db table 7. frequency response of lpf
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 20 - figure 10 shows an input buffer circuit example 2. (1 st order hpf; fc=0.66hz, 1 st order lpf; fc=590khz, gain= ? 14db). the analog signal is able to input through xlr or bnc connectors. (short jp1 and jp2 for bnc input, open jp1 and jp2 for xlr input). the input level of this circuit is +/ ? 12.1vpp (ak5394a: +/ ? 2.4vpp typ.). when using this circuit, analog characteristics at fs=48khz is dr=123db, s/(n+d)=94db. 180 100 bias vin+ ak5394 ain+ - + va 1.0n 1k 10k 22u 180 vin- ak5394 ain- - + 1k 22u 10k 0.1u 10u 4.7k 4.7k xlr bnc - + 4.7k 4.7k jp2 jp1 njm5534 njm5534 njm5534 2.4vpp 2.4vpp 12.1vpp 12.1vpp figure 10. analog input buffer circuit example 2 fin 1hz 10hz frequency response ? 1.56db ? 0.02db table 8. frequency response of hpf fin 20khz 40khz 80khz 6.144mhz frequency response ? 0.005db ? 0.02db ? 0.08db ? 20.4db table 9. frequency
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 21 - 5. measurement example figure 11 plot is the thd+n vs input level with circuit figure 9 and circuit figure 10. x-axis is input level, y-axis is thd+n (ratio). measurement condition ta=25 c; va=5.0v; vd=3.3v; agnd, bgnd, dgnd=0v; fs=48khz; input frequency=1khz; 24 bit output; measurement frequency =10hz 20khz; dfs0=?l?, dfs1=?l?, vref capacitors=1000f measured by audio precision system two. akm ak5394a thd+n vs input level last.at2c -30 -2 -28 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 dbr -120 -80 -117.5 -115 -112.5 -110 -107.5 -105 -102.5 -100 -97.5 -95 -92.5 -90 -87.5 -85 -82.5 d b figure 11. thd+n(ratio) vs. input level figure 12 shows the relationship between thd+n and frequency with capacitors on table 4. input circuit uses figure 9. measurement condition ta=25 c; va=5.0v; vd=3.3v; agnd, bgnd, dgnd=0v; fs=48khz; 24 bit output; bw=10hz 20khz; dfs0=?l?, dfs1=?l?, measured by audio precision system two. akm ak5394a thd+n vs frequency last.at2c -130 -60 -125 -120 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -65 d b f s 10 20k 20 50 100 200 500 1k 2k 5k 10k hz figure 12. thd+n vs. frequency figure 10 fi g ure 9 10f 100f 220f 470 f 1000 f
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 22 - 6. noise floor of ak5394a the ak5394a has a sprious noise of about ? 135dbfs on the noise floor of lch output at no signal input. when this noise causes a trouble in system, it can be removed by adding a minute offset to the analog inputs of both channels externally using a circuit as figure 13. the relationship between the frequency range (f t ) of the sprious noise to be removed and the adding offset voltage (v of ) is f t [khz] = 20 x v of [mv] ? 20. the example is shown in table 10. sprious noise frequency offset voltage 0 20khz +2mv 0 40khz +3mv 0 80khz +5mv table 10. sprious noise frequency vs. offset voltage a resistor, r in figure 13 should be 8 ? to add an offset of 2mv to the analog inputs. the relationship between r and v of is shown by the following equation. ] [ 5 20 v r k r v of + = an offset voltage of the op-amps should be considered in the actual circuit. for example, when removing the sprious noise of 20khz or less, the adding offset voltage should be 2+2=4mv if the op-amp has an offset of +/ ? 2mv. in this case, the dynamic range of the adc output decreases 4mv. - + 91 3.3k 620 - + 91 620 68 10 + 10k 10k 0.1 bias+ 5v bias+ 1n 3.3k 1n bias- 2.2n 68 xlr vin+ vin- njm5534 njm5534 ak5394a ain+ ak5394a ain- r bias- figure 13. removing the sprious noise circuit
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 23 - package 0-10 0.10 0.15-0.05 1.095typ 18.7 0.3 28pin sop (unit: mm) 7.5 0.2 0.75 0.2 +0.1 10.4 0.3 2.2 0.1 1.27 0.12 m +0.1 0.1-0.05 0.4 0.1 ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
asahi kasei [ak5394a] ms0137-e-01 2002/07 - 24 - marking akm AK5394AVS xxxbyyyyc contents of xxxbyyyyc xxxb: lot # (x : numbers, b : alphabet ) yyyyc: data code (y : numbers, c : alphabet) important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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